FIG. 1 is a block diagram showing an example of a conventional prior art arrangement of an electronic data transfer apparatus. In FIG. 1, numeral 1 denotes a main device, such as a CRT device, and numeral 2 denotes an input/output requesting device, such as an input/output controller. The main device 1 and the input/output requesting device are connected to each other through a data bus 3. The data bus 3 includes an input request signal line 3A for transmitting a data input request from the input/output requesting device 2 to the main device, an output request signal line 3B for transmitting a data output request, a status request signal line 3C for requesting status information, such as "busy" or "ready", from the main device 1, and data signal lines 3D for transmitting data between the two devices. The main device 1 may also contain a status signal generator (not shown) for indicating the actual status information to an external device.
In the prior art example, the input/output requesting device 2 applies predetermined requests through the input request signal line 3A, the output request signal lie 3B, and the status request signal line 3C in the data bus 3 to the main device 1 so as to input and output data to and from the main device 1 in response to the status of the main device 1. The input/output requesting device 2 must complete the input or output operation of the predetermined data within a period that the main device 1 is ready, i.e., within a period that the input or output operation is enabled. Thus, the input/output requesting device 2 generates a predetermined status request to thereby read corresponding status information from the main device 1 and inputs or outputs the predetermined data after confirming that the main device 1 has entered the ready period. However, according to this method, there is a possibility that the main device 1 might enter a busy period, i.e., a period where the data input or output operation is disabled while the predetermined data are transferred between the two devices, causing interference in the main device 1. From this, it is necessary for the input/output requesting device 2 to synchronize the transfer of input or output data with the start of the ready period of the main device 1 and to terminate the transfer when the main device 1 enters a busy period.
FIG. 2 is a detailed diagram of a prior art CRT main device. In FIG. 2, a synchronous signal generator 5 supplies a synchronous signal to the CRT 7 for enabling and disabling data display. The memory 6 includes a WRITE ENABLE port receiving the input request signal 3A to control data input and output at the I/O DATA port. When the input request signal 3A is valid, data are written into the memory 6. Otherwise, the data stored in the memory 6 are read out and displayed on the CRT 7 or output to the input/output requesting device 2. At the same time, a buffer 8 transfers data from the input/output requesting device 2 to the memory 6. When the output request signal 3B is valid, a buffer 9 transfers data in the memory 6 to the input/output requesting device 2 on the data signal lines 3D. When the status request signal 3C is valid, a buffer 10 transfers the synchronous signal as a status signal to the input/output requesting device 2 on the data signal lines 3D.
As can be seen, when both the input request signal 3A and the output request signal 3B are invalid, data are read from the I/O DATA port of the memory 6 and displayed on the CRT 7 in accordance with the synchronous signal from the synchronous signal generator 5. When the output request signal 3B is valid, data to be output to the input/output requesting device 2 are read out of the memory 6 at the same I/O DATA port instead of being displayed on the CRT 7 and the CRT display is subjected to undesirable interference. Furthermore, when the input request signal 3A is valid, data from the input/output requesting device 2 enters the I/O DATA port of the memory 6 to be stored, interferes with data to be displayed on the CRT 7, and causes undesirable interference in the main device 1. However, as shown in FIG. 3, since the synchronous signal generated by the synchronous signal generator 5 includes periods in which data will not be displayed, there is no interference to the CRT 7 when the input and output request signals 3A and 3B are valid during this nondisplay period. These non-display periods can be discerned if the synchronous signals are read out as the status signal. Accordingly, the input/output operation is operable only during the non-display periods.
The above-described CRT device is a representative example of the main device 1 in which the ready period is a blanking period corresponding to a period when data can be input and output and the busy period is a display period corresponding to a period when data are displayed on the CRT device. The length of the busy period is generally longer than that of the ready period and, when data are input or output within the ready period, the data to be dis
Payed within the busy period are reliably supplied to the CRT device. However, if the data input or output are, for example, started at or near the end of the ready period, the period will shift to the busy period before the input or output operation is finished, and interference will be displayed on the screen of the CRT device.
The flow chart in FIG. 4 shown an example of an algorithm illustrating operating steps devised to eliminate the above drawback. When the input/output requesting device 2 determines that an input/output operation is to be performed, it sends a status request to the main device 1, and the status signal of the main device 1 is input in step S32. Step S33 determines whether the main device 1 has entered a ready period. If NO is determined in step S33, the operation is shifted to step S34. If YES is determined in step S33, the operation is returned to step S32. The status signal of the main device 1 is input in step S34 and whether the main device 1 has entered a busy period is determined in step S35. If YES is determined in step S35, the operation is returned to step S34, but if NO is determined in step S35, the operation is shifted to step S36. As the predetermined data are input or output, the operation is ended at step S37.
The data input to or output from the main device 1 is started at or near the starting point of the ready period according to the algorithm represented in FIG. 4. In other words, the data input/output is started substantially synchronously with the starting point of the ready period of the main device 1.
The main device in the above prior art example is constructed so that ready periods and busy periods are taken at a certain repetitive ratio. This is a drawback in that, when the data input/output is not completed within the ready period, interference is generated in the busy period. Even if a main device is prepared in which data input/output is always enabled, its function cannot be utilized unless the algorithm in FIG. 4 is modified. Therefore, another drawback arises in which data input/output speed cannot be improved.